The present invention relates in general to the field of memories. More particularly, the present invention relates to a BIMOS memory cell having improved read speed as a result of having a separate NPN transistor to provide additional drive for the read cycle.
The basic CMOS cross coupled latch, which is well known in the art, forms a basic static storage element. In such a device both the reading and writing of the cell have in the past been accomplished by a bit line coupled directly to the cell. This bit line is ordinarily coupled to a number of separate cells and therefore represents a fairly high capacitive load. The read time would therefore be relatively long in that the memory cell itself would be relied upon to transfer current to the high capacitive load bit line. The CMOS memory cell does not ordinarily provide a high current which could charge the capacitive load of the bit line rapidly. The read times have therefore been relatively high for those devices which couple the bit line directly to the CMOS cross coupled latch memory cell.